用verilog HDL设计一个三分频器，输入时钟占空比为1:1

Question

如题所述

Answer 1

我想一下
=======================================================================
module div3(clk,clk_3);
input clk;
output clk_3;

reg [1:0] countp;
reg [1:0] countn;
reg clk_3p;
reg clk_3n;

always@(posedge clk) begin
if(countp<=2'd1) begin
clk_3p<=1'b1;
countp<=countp+2'd1;
end
else if(countp==2'd2) begin
clk_3p<=1'b0;
countp<=2'd0;
end
end

always@(negedge clk) begin
if(countn<=2'd1) begin
clk_3n<=1'b1;
countn<=countn+2'd1;
end
else if(countn==2'd2) begin
clk_3n<=1'b0;
countn<=2'd0;
end
end

assign clk_3=(clk_3p&&clk_3n)?1'b1:1'b0;
endmodule
======================================================================
我已经测试了
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Answer 2

//任意奇数分频器，只需要将n改为你想要的奇数即可。
module any_odd_div (clkdiv,clk);

output clkdiv; //输出分频信号
input clk; //时钟信号
reg[2:0]cnt1,cnt2;//计数器1，计数器2
reg clk_temp1,clk_temp2;
parameter n = 7; //7分频

always @(posedge clk)
begin
if(cnt1 == n-1)
begin cnt1 <=3'b000; end
else
begin cnt1 <= cnt1 +1'b1; end
if(cnt1 ==3'b000)
begin clk_temp1 =1'b1; end
if(cnt1 ==(n-1)/2)
begin clk_temp1 =0; end
end

always @(negedge clk)
begin
if(cnt2 == n-1)
begin cnt2 <=3'b000; end
else
begin cnt2 <=cnt2 +1'b1; end
if(cnt2 ==3'b000)
begin clk_temp2 =1; end
if(cnt2 ==(n-1)/2)
begin clk_temp2 =0; end
end

assign clkdiv = clk_temp1 | clk_temp2;

endmodule