用verilog HDL设计一个五三分频器，输入时钟占空比为1:1

Question

如题所述

Answer 1

还是去计数，计上升沿和下降沿次数。五三分频器，不明白

Answer 2

module divider(
clk_in,
rst,
mode,
clk_out
);

input clk_in;
input rst;
input mode;
output clk_out;

reg [3:0] cnt1;
reg [3:0] cnt2;
wire level_gen;
reg level_chg;
wire [1:0] mode;
reg clk_out;

always@(posedge clk_in or negedge rst)
begin
if(rst == 1'b0)begin
cnt1 <= 4'h0;
end
else if(cnt2 >= 4'h5)begin
cnt1 <= 4'h1;
end
else begin
cnt1 <= cnt1 + 1'b1;
end
end

always@(posedge clk_in or negedge rst)
begin
if(rst == 1'b0)begin
cnt2 <= 4'h0;
end
else if(cnt2 == 4'h8)begin
cnt2 <= 4'h1;
end
else begin
cnt2 <= cnt2 + 1'b1;
end
end

assign level_gen = ((cnt1 == 4'h5) || (cnt2 == 4'h8)) ? 1'b1 : 1'b0;

always@(posedge clk_in or negedge rst)
begin
if(rst == 1'b0)begin
level_chg <= 1'b0;
end
else if(level_gen == 1'b1)begin
level_chg <= ~level_chg;
end
end

always@(*)
begin
if(rst == 1'b0)begin
clk_out = 1'b0;
end
else if(mode == 2'b10)begin
clk_out = level_chg;
end
else if(mode == 2'b01)begin
clk_out = ~level_chg;
end
else begin
clk_out = 1'b0;
end
end

endmodule本回答被提问者采纳