VHDL 设计一个6选1数据选择器 输出端Y为4位，端口命名如下

Question

SL:IN std_logic_vector (3 downto 0)
SH:IN std_logic_vector (2 downto 0)
ML:IN std_logic_vector (3 downto 0)
MH:IN std_logic_vector (2 downto 0)
HL:IN std_logic_vector( 3 downto 0)
HH:IN std_logic_vector (1 downto 0)
Y:out std_logic_vector( 3 downto 0)
S:in std_logic_vector (2 downto 0)

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mux6_1 is
port(
SL:IN std_logic_vector (3 downto 0);
SH:IN std_logic_vector (2 downto 0);
ML:IN std_logic_vector (3 downto 0);

MH:IN std_logic_vector (2 downto 0);
HL:IN std_logic_vector( 3 downto 0);
HH:IN std_logic_vector (1 downto 0);
Y:out std_logic_vector( 3 downto 0);
S:in std_logic_vector (2 downto 0)
);
end;

architecture behave of mux6_1 is
begin
Y<= SL when s="000" else
'0' & SH when s="001" else
ML when s="010" else
'0' & MH when s="011" else
HL when s="100" else
'0' & '0' & HH when s="101" else
NULL;
end behave;