用VHDL语言IF语句来实现4选1数据选择器,亲们我很着急啊，有没有好心人啊，帮帮我 啊

Question

如题所述

Answer 1

entity mux4_1 is
port ( a,b,c,d: in std_logic; --4位输入信号，数据类型自己改
s1,s2: in std_logic; --选择信号
y : out std_logic ); --输出信号，数据类型和输入应一致
end entity;
architecture bhv of mux4_1 is
signal s :std_logic_vector(1 downto 0);
begin
s<=s1&s2;
process(s,a,b,c,d)
begin
if s="00" then y<=a;
elsif s="01" then y<=b;
elsif s="10" then y<=c;
else y<=d;
end if;
end process;
end bhv;