求教：利用VHDL设计一个4选1数据选择器，然后用生成语句设计双四选一数据选择器

Question

如题所述

Answer 1

提问时间：2011-10-22 20:26:17

library ieee; use ieee.std_logic_1164.all; entity xzq4 is port(i0, i1, i2, i3:in std_logic_vector(15 downto 0); s0, s1: in std_logic; y : out std_logic_vector(15 downto 0)); end xzq4; architecture rtl of xzq4 is signal sel : std_logic_vector (1 downto 0); begin sel<=s1 & s0;- with sel select y<=i0 when "00", i1 when "01", i2 when "10", i3 when others; end rtl;本回答被网友采纳

Answer 2

你是宁大信息学院的吧,我待会儿就要上课了