求一个16选1数据选择器的VHDL描述，要求是用4选1的数据选择器构成，谢谢了

Question

如题所述

Answer 1

4选1的数据选择器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux41 is
port(a,b,c,d:in std_logic;
s:in std_logic_vector(1 downto 0);
y:out std_logic);
end;
architecture one of mux41 is
begin
y<= a when s=0 else
b when s=1 else
c when s=2 else
d;
end;
16选1数据选择器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux161 is
port(ain,bin,cin,din,ein,fin,gin,hin,iin,jin,kin,lin,min,nin,oin,pin:in std_logic;
s1,s2:in std_logic_vector(1 downto 0);
y:out std_logic);
end;
architecture one of mux161 is
component mux41
port(a,b,c,d:in std_logic;
s:in std_logic_vector(1 downto 0);
y:out std_logic);
end component;
signal e,f,g,h:std_logic;
begin
u1:mux41 port map(ain,bin,cin,din,s1,e);
u2:mux41 port map(ein,fin,gin,hin,s1,f);
u3:mux41 port map(iin,jin,kin,lin,s1,g);
u4:mux41 port map(min,nin,oin,pin,s1,h);
u5:mux41 port map(e,f,g,h,s2,y);
end;本回答被提问者采纳