verilog中如何调用fifo做50个信号延迟

Question

如题所述

Answer 1

50个clk延迟吧 将fifo写使能始终置1 当count==50的时候 再把fifo读使能始终置1 这样就可以使某个信号延迟50个clk了本回答被网友采纳

Answer 2

he had no idea where she came from or how she worked her magic.