利用VHDL设计一个6选1选择器(6位被选信号输入;3位选择控制,1位选择信号输出）

Question

使能输入端EN，当其为低电平时，选择器工作，否则不工作。

Answer 1

library ieee;
use ieee.std_logic_1164.all;
entity mux_6_1 is
port(en_n: in std_logic;
sel: in std_logic_vector(2 downto 0);
signal_in: in std_logic_vector(5 downto 0);
y: out std_logic);
end entity mux_6_1;
architecture behave of mux_6_1 is
begin
process(en_n,sel,signal_in)
begin
if en_n='0' then
case sel is
when "000" => y <= signal_in(0);
when "001" => y <= signal_in(1);
when "010" => y <= signal_in(2);
when "011" => y <= signal_in(3);
when "100" => y <= signal_in(4);
when "101" => y <= signal_in(5);
when others => y <= 'Z';
end case;
else
y <= 'Z';
end if;
end process;
end architecture behave;
你未说明选择器不工作的具体含义，所以上述描述将不工作描述为输出高阻态'Z'。