设计4选1数据选择器的VHDL程序，设有使能信号EN控制。急求 程序要全部给我 谢谢

Question

如题所述

Answer 1

LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITY mux_4_1 IS
PORT(en: IN Std_logic;
sel: IN Std_logic_vector(1 DOWNTO 0);
a, b, c, d: IN Std_logic;
y: OUT Std_logic);
END mux_4_1;
ARCHITECTURE behavl_case OFmux_4_1 IS
BEGIN
p_case: PROCESS（en, sel, a, b, c, d）
BEGIN
IF en='1' THEN
CASE sel IS
WHEN "00" => y <= a;
WHEN "01" => y <= b;
WHEN "10" => y <= c;
WHEN "11" => y <= d;
WHEN OTHERS => y <= 'Z';

END CASE;
ELSE
y <= 'Z';
END IF;
END PROCESS p_case;
END behavl_case;