第1个回答 2014-05-25
ENTITY mux4 IS
PORT( d3,d2,d1,d0: IN bit;
s1,s0: IN bit;
y: OUT bit);
END mux4;
ARCHITECTURE one OF mux4 IS
BEGIN
PROCESS(d3,d2,d1,d0,s1,s0)
BEGIN
CASE s1&s0 IS
WHEN "11" => y <= d3;
WHEN "10" => y <= d2;
WHEN "01" => y <= d1;
WHEN "00" => y <= d0;
END CASE;
END PROCESS;
END one;本回答被提问者采纳