2. 利用VHDL语言描述一个带有同步复位功能的上升沿触发D触发器

Question

写出其VHDL程序

Answer 1

核心就是reset是用clk来同步，即只能在clk的沿到来时reset。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity dff_sr is
port(
clk: in std_logic;
rst_n: in std_logic;
din: in std_logic;
qout: out std_logic);
end dff_sr;

architecture str of dff_sr is
begin
process(clk,rst_n)
begin
if clk'event and clk = '1' then
if rst_n = '1' then
qout <= '0'
else
qout <= din;
end if;
end if;
end process;
end str;