用VHDL语言 编写2输入与门、 2输入或门、 2输入异或门及非门的设计

Question

如题所述

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GATE IS
PORT(A,B:IN STD_LOGIC;
YAND,YOR,YXOR,YNOT:OUT STD_LOGIC);
END GATE;
ARCHITECTURE ART OF GATE IS
BEGIN
YAND<=A AND B;
YOR<=A OR B;
YXOR<=A XOR B;
YNOT<=A NOT B;
END ART;

Answer 2

订正下，楼上YNOT<=NOT A;