vhdl编写四路二输入异或门

Question

如题所述

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sl IS
PORT(A1,B1,A2,B2,A3,B3,A4,B4 : IN STD_LOGIC
Y1,Y2,Y3,Y4 : OUT STD_LOGIC);
END ENTITY
ARCHITECURE one OF sl IS
BEGIN
Y1<=A1 XOR B1;
Y2<=A2 XOR B2;
Y3<=A3 XOR B3;
Y4<=A4 XOR B4;
END ARCHITECURE one;

Answer 2

异或可以用 xor 符合直接实现的哦