怎么用VHDL语言编写16输入异或门

Question

如题所述

Answer 1

循环的方式：--------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;entity xor_16 is
port(DATAIN : in std_logic_vector(15 downto 0);
DATAOUT : out std_logic);
end xor_16;architecture behave of xor_16 is
signal TMP : std_logic;
begin
process(DATAIN)
begin
TMP<=DATAIN(0);
for n in 1 to 15 loop
TMP<=TMP xor DATAIN(n);
end loop;
DATAOUT<=TMP;
end process;
end behave;--------------------------------------------------------------------本回答被网友采纳