利用状态机的VHDL描述方法设计一个序列检测器,要求8个数中，有3个或3个以上的1时输出为1，否则为0。急啊

Question

如题所述

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xulie is
port(clk,reset:in std_logic;
data:in std_logic;
result:out std_logic);
end entity;
architecture art of xulie is
tyqe states is(s0,s1,s2);
signal state:states;
process(clk,reset,data)
variable cnt,count:integer range 0 to 8;
begin
if reset='1' then
state<=s0;result<='0';
elsif clk'event and clk='1' then
case state is
when s0=>cnt:=0;count:=0;state<=s1;
when s1=>if count=8 then
state<=s2;
else count:=count+1;
state<=s1;
if data='1' then
cnt:=cnt+1;
end if;
end if;
when s2=>if cnt>=3 then
result<='1';
else result<='0';
end if;
state<=s0;
when others=>state<=s0;
end case;
end if;
end process;
end art;

Answer 2

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xulie is
port(clk,reset:in std_logic;
data:in std_logic;
result:out std_logic);
end entity;
architecture art of xulie is
tyqe states is(s0,s1,s2);
signal state:states;
process(clk,reset,data)
variable cnt,count:integer range 0 to 8;
begin
if reset='1' then
state<=s0;result<='0';
elsif clk'event and clk='1' then
case state is
when s0=>cnt:=0;count:=0;state<=s1;
when s1=>if count=8 then
state<=s2;
else count:=count+1;
state<=s1;
if data='1' then
cnt:=cnt+1;
end if;
end if;
when s2=>if cnt>=3 then
result<='1';
else result<='0';
end if;
state<=s0;
when others=>state<=s0;
end case
end if
end process