用vhdl语言设计一个序列信号检测器

Question

利用状态机的VHDL描述方法设计一个序列信号检测器，要求连续输入3个或3个以上的1时输出为1，否则输出为0

Answer 1

library ieee;
use ieee.std_logic_1164.all;
entity detector is
port(clk,reset:in std_logic;
state_inputs: std_logic;
q:out std_logic);
end detector;
architecture behav of detector is
type fsm_st is(st0,st1,st2,st3);
signal current_state,next_state:fsm_st;
begin
reg:process(clk,reset)
begin
if reset='1'then current_state<=st0;
elsif clk'event and clk='1' then
current_state<=next_state;
end if;
end process;
com:process(current_state,state_inputs)
begin
case current_state is
when st0=>q<='0';
if
state_inputs='0'then next_state<=st0;
elsif state_inputs='1'then next_state<=st1;
end if;
when st1=>q<='0';
if state_inputs='0'then next_state<=st0;
elsif state_inputs='1'then next_state<=st2;
end if;
when st2=>q<='0';
if state_inputs='0'then next_state<=st0;
elsif state_inputs='1'then next_state<=st3;
end if;
when st3=>q<='1';
if state_inputs='0'then next_state<=st0;
elsif state_inputs='1'then next_state<=st3;
end if;
end case;
end process;
end behav;

Answer 2

用状态机来写，具体还是自己写的比较好