哪位高人可以指点下我的verilog程序，实现5分频占空比为50%

Question

源程序如下：module fenpin5(clk,rst,clk1,clk2,clk_out);output clk1,clk2;output clk_out;input clk,rst;reg clk1,clk2;reg clk_out;wire clk,rst;parameter n=0;parameter i=0;assign clk_out=clk1|clk2;always @(posedge clk)if(rst)beginclk1<=0;n<=0;endelse if(n==2) begin n<=n+1; clk1<=~clk1; endelse if(n==4) begin n<=0; clk1<=~clk1; endelse n<=n+1;always@(negedge clk)if(rst)clk2<=0;i<=0;else if(i==2) begin i<=i+1; clk2<=~clk2; endelse if(i==4) begin i<=0; clk2<=~clk2 endelse i<=i+1;endmodule

Answer 1

很多地方有问题，begin...end的用法再去查查，还有wire和reg，下面是参考code：
module fenpin5(clk,rst,clk1,clk2,clk_out);
output clk1,clk2;
output clk_out;
input clk,rst;

reg clk1,clk2;
// reg clk_out;
wire reg_out;

wire clk,rst;

reg [3:0] n, i;

assign clk_out=clk1|clk2;
always @(posedge clk)
if(rst) begin
clk1<=0;
n<=0;
end
else if(n==2) begin
n<=n+1;
clk1<=~clk1;
end
else if(n==4) begin
n<=0;
clk1<=~clk1;
end
else n<=n+1;

always@(negedge clk)
if(rst) begin
clk2<=0;
i<=0;
end
else if(i==2) begin
i<=i+1; clk2<=~clk2;
end
else if(i==4) begin
i<=0; clk2<=~clk2 ;
end
else i<=i+1;

endmodule