用VHDL语言用程序方法设计一个占空比为50%的11分频电路

Question

如题所述

Answer 1

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shukong is
port{
clk250:in std_logic;
d:in std_logic_vector(3 downto 0);
divclk:out std_logic
};
end entity;
architecture be of shukong is
variable full:std_logic;
variable clk1:std_logic_vector(3 downto 0);
begin
process(clk250)
begin
if clk250'event and clk = '1' then
if clk1 = "1111" then
clk1 <= d;
else clk1 := clk1 + 1;
end if;
end if;
end process;

process(clk1)
if clk1 = 1 then full := 0;
else full := 1;
end if;
end process;
divclk <= full;
end architecture;
这是个数控分频，11分频只要d赋值为“1011”就可以了