verilog HDL 里pullup.pulldown怎么用的

Question

如题所述

Answer 1

`timescale 1ns/1ps
module test();
reg a;
reg d;
wire b;
wire c;
wire e;
reg clk;

always #10 clk = ~clk;

initial begin
clk =1'b0;
d = 1'bx;
#100;
a = 1'b1;
#100;
a = 1'b0;
#100;
d = 1'bz;
#100;
$finish;
end
pulldown(b);
pulldown(c);
pulldown(e);
assign b = a;
assign e = d;

always@(posedge clk) begin
$display("@%0t a = %b b = %b c= %b d = %b e = %b ",$realtime,a,b,c,d,e);
end
endmodule

Answer 2

关键字
pullup
和
pulldown
用法。有用例如下：
wire
scl
；
wire
sda
；
/*
实例化各子模块
*/
pullup
p1(scl);
//
pullup
scl
line
pullup
p2(sda);
//
pullup
sda
line
所谓上下拉应该是对当前无驱动的线才会有作用。本回答被提问者和网友采纳