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module div(
input I_enable,
input [1:0] I_select,
input I_clk_100m,
output reg O_clk_div = 1'b0
);
wire [5:0] W_div_cnt;
reg [5:0] R_cnt == 6'd0;
always@* begin
case(I_select)
2'b00: W_div_cnt <= 6'd4;
2'b01: W_div_cnt <= 6'd9;
2'b10: W_div_cnt <= 6'd24;
2'b11: W_div_cnt <= 6'd49;
endcase
end
always@(posedge I_clk_100m) begin
if(!I_enable) begin
R_cnt <= 6'd0;
O_clk_div <= 1'b0;
end
else if(R_cnt == W_div_cnt) begin
R_cnt <= 6'd0;
O_clk_div <= !O_clk_div;
end
else begin
R_cnt <= R_cnt + 1'b1;
end
end
endmodule