多路选择器的2选1

Question

如题所述

Answer 1

EDA和VHDL代码
library ieee
use ieee.std_logic_1164.all;
entity data is
port(in0,in1,se1:in std_logic;
output:out std_logic);
architecture one of data is
begin
output<=in0 when se1='0'else in1;
end architecture one;