第2个回答 2011-09-24
module CLOCK
(
clk,clk2,RSTn
)
input clk;
output clk2;
reg rclk2;
reg[3:0] count1
always @ (posedge clk or negedge RSTn)
begin
if(!RSTn)
count1<=4'b0;
clk2<=1'b0
else if( count1<=4'd3)
rclk2<=~rclk2;
else count1<=count1+1'b1;
end
assign clk2=rclk2;
endmodule