用VHDL设计一个双进程状态机,
状态0时如果输入“10”则转化为另一状态,否则输出‘1001’;
状态1时如果输入“11”则转化为下一状态,否则输出‘0101’;
状态2市如果输入“01”则转化为下一状态,否则输出‘1100’;
状态3时如果输入“00”则转化为状态0,否则输出'0010';
复位状态为0
VHDL设计一个双进程状态机,原程序如下(后面的图是仿真结果):
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dou_state is
port(clk,rst : in std_logic;
din : in std_logic_vector(1 downto 0);
dout : out std_logic_vector(3 downto 0));
end dou_state;
architecture arch of dou_state is
type state_type is (s0,s1,s2,s3);
signal state : state_type;
begin
P1: process(clk,rst)
begin
if rst='0' then
state <= s0;
dout <= "0000";
elsif clk'event and clk='1' then
case state is
when s0 =>
if din = "10" then
state <= s1;
else
state <= s0;
dout <= "1001";
end if;
when s1 =>
if din = "11" then
state <= s2;
else
state <= s1;
dout <= "0101";
end if;
when s2 =>
if din = "01" then
state <= s3;
else
state <= s2;
dout <= "1100";
end if;
when s3 =>
if din = "00" then
state <= s0;
else
state <= s3;
dout <= "0010";
end if;
when others =>
NULL;
end case;
end if;
end process;
end arch;