同步复位JK触发器VHDL源程序如下，仿真结果和仿真后电路图如图所示
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--*-------------entity---------------------*--
entity JK is
port(clk : in std_logic;
set : in std_logic;
J,K : in std_logic;
Q : out std_logic;
Q1 : out std_logic);
end JK;
--*--------------end-----------------------*--
--*---------------architecture----------------------*--
architecture arch of JK is
signal Q_pre : std_logic;
begin
P1 : process(clk,set)
begin
if clk'event and clk='1' then
if set='0' then
Q_pre <= '0';
elsif J='0'and K='0' then
Q_pre <= Q_pre;
elsif J='0'and K='1'then
Q_pre <= '0';
elsif J='1'and K='0'then
Q_pre <= '1';
elsif J='1'and K='1'then
Q_pre <= not Q_pre;
else
NULL;
end if;
end if;
end process P1;
--*--------------------------------------------------*--
P2 : process(Q_pre)
begin
Q <= Q_pre;
Q1<= not Q_pre;
end process;
end arch;
--*------------------------end-----------------------*--
