Verilog问题 求助 急急急！！！！！

Question

用D触发器设计设计8421BCD吗计数器 0到999 要写出结构描述的verilog语言 求求高手了 帮小弟一个忙吧
把测试文件也写上

Answer 1

module counter (count, clk, reset);
output [9:0] count;
input clk, reset;
reg [9:0] count;
always @ (posedge clk or posedge reset)
if (reset)
count <= 10'b0;
else
count <= count + 10'b1;
endmodule

测试文件
`timescale 10ns/1ns
module tcounter;
reg clk, reset;
wire [7:0] count;
counter dut (count, clk, reset);
initial // Clock generator
begin
clk = 0;
forever #10 clk = !clk;
end
initial
begin
reset = 0;
#5 reset = 1;
#4 reset = 0;
end
endmodule