module temperature (clk,dq,
d,cont,temp
);
input clk; //时钟1MHZ
input dq; //数字温度串行输入端口
output d; //控制信号输出端口
output cont; //三态门控制信号
output [9:0] temp; //10为温度值并行输出端口
reg d;
reg cont;
reg [9:0] temp;
reg data;
reg [6:0] num; //时隙计数，70个时钟周期为一个时隙
reg [6:0] count; //一次温度转换和输出技术，70个时隙
reg [9:0] t;
always @(posedge clk)
begin
num = num + 1 ;
if (num > 7'b1000100)
begin num = 7'b0000000;
if (count == 7'b1001011)
begin count = 7'b0000000 ; end
else
begin count = count + 1 ; end
end
else
begin num = num + 1 ; end
//---------------------------------------------------------------
if (count >= 7'b0000000 && count <= 7'b0000110) //reset脉冲
begin data = 0 ; cont = 0 ; end
//---------------------------------------------------------------
else if (count > 7'b0000110 && count <= 7'b0001101) //presenc脉冲
begin cont = 0 ; end
//---------------------------------------------------------------
else if (count == 7'b0001110 || count == 7'b0001111 || count == 7'b0010010 || count == 7'b0010011) ; //skip‘0’空隙
begin
if (num >= 7'b0000000 && num < 7'b0111100)
begin data = 0 ; cont = 1 ; end
else
begin cont = 0 ; end
end
//---------------------------------------------------------------
else if (count == 7'b0010000 || count == 7'b0010001 || count == 7'b0010100 || count == 7'b0010101) ;
begin
if (num >= 7'b0000000 && num < 7'b0001010)
begin data = 0 ; cont = 1 ; end
else
begin cont = 0 ; end
end
//---------------------------------------------------------------
else if (count == 7'b0010110 || count == 7'b0010111 || count == 7'b0011001 || count == 7'b0011010 || count == 7'b0011011 || count == 'b0011101) ; //convert'0'
begin
if (num >= 'b0000000 && num < 'b0111100)
begin data = 0 ; cont = 1 ; end
else
begin cont = 0 ; end
end
//---------------------------------------------------------------
else if (count == 'b0011000 && count == 'b0011100)
begin
if (num >= 'b0000000 && num < 'b00011100)
begin data = 0 ; cont = 0 ; end
else
begin cont = 0 ; end
end
end
endmodule