用verilog编写源代码和测试程序

Question

编写一个4 位计数器，计数器为异步复位，复位后计数器的值为0，计数顺
序为：0->2->3->4->7->9->10->11->12->13->14->15->0

Answer 1

下面的代码我已经用modelsim仿真过了，没有问题。
module count(out,clk,rst); //源程序
input clk,rst;
output[3:0] out;

reg[3:0] out;

initial out=4'd0;

always @(posedge clk or negedge rst)
begin
if(!rst) out=4'd0;
else
begin
out=out+4'd1;
if(out==4'd1||out==4'd6||out==4'd8) out=out+4'd1;
if(out==4'd5) out=out+4'd2;
end
end

endmodule

`timescale 1ns/1ns //测试程序
`include "count.v"
module count_tp;
reg clk,rst;
wire[3:0] out;
parameter DELY=100;
count mycount(out,clk,rst);
always #(DELY/2) clk=~clk;
initial
begin
clk=0;rst=1;
#(DELY*5) rst=0;
#DELY rst=1;
#(DELY*20) $finish;
end
initial $monitor($time,,,"clk=%d rst=%d out=%d",clk,rst,out);
endmodule

Answer 2

这种顺序不能用计数器实现吧