verilog中总是在赋值的地方出错

Question

module U3(din,clk,out0,out1,out2,out3);
input din,clk;
output out0,out1,out2,out3;
reg out0,out1,out2,out3;
always@(posedge clk);
begin
out3=out2;
out2=out1;
out1=out0;
out0=din;
end
endmodule

** Error: D:/modelsim10/examples/T3~.v(7): near "<=": syntax error, unexpected <=, expecting IDENTIFIER or TYPE_IDENTIFIER

Answer 1

out3<=out2;
out2<=out1;
out1<=out0;
out0<=din;