verilog简单的赋值问题出错了

Question

一个流水灯程序如下：下面那个outdat <= outdat+1;然后端口就是乱码不是+1的结果，而outdat = 8'b1010_1010;却是正常的，这个事怎么不是
module LED(outdat,clk);
input clk;
output [7:0] outdat;
reg [7:0] outdat =8'b1000_0001;
reg [31:0] count = 0;
reg led1 = 0;
always @(posedge clk)
begin
if(count < 32'd30_000_000)
count <= count+1;
else
count <= 0;
end
always @(posedge clk)
begin
if(count == 32'd30_000_000)
led1 <= ~led1;
end
always @(posedge clk)
begin
if(led1)
//outdat <= outdat+1;
outdat = 8'b1010_1010;
end
endmodule

Answer 1

把最后
always @(posedge clk)
begin
if(led1)
//outdat <= outdat+1;
outdat = 8'b1010_1010;
end
改成
always @(led1)
begin
outdat <= outdat+1;
end
这样就可以了。本回答被网友采纳