第1个回答 推荐于2016-03-06
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is port (
clkin:in std_logic;
rest:in std_logic;
clk6fen:out std_logic);
end;
architecture fenpins of fenpin is
signal counter:std_logic_vector(0 to 2);
begin
process(clkin,counter,rest) begin
if rest='0' then
counter<="000";
elsif clkin'event and clkin='1'then
if counter<5 then
counter<=counter+1;
if counter<3 then
clk6fen<='1';
else
clk6fen<='0';
end if;
else
counter<="000";
end if;
end if ;
end process;
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