verilog中如何读取文本文件中的十进制数据作为测试激励信号?

Question

如题所述

Answer 1

试试：
$readmemb ( " file_name " , memory_name [ , start_addr [ , finish_addr ] ] ) ;
$readmemh ( " file_name " , memory_name [ , start_addr [ , finish_addr ] ] ) ;

Answer 2

$readmemb ( " file_name " , memory_name [ , start_addr [ , finish_addr ] ] ) ;
$readmemh ( " file_name " , memory_name [ , start_addr [ , finish_addr ] ] ) ;本回答被提问者和网友采纳

Answer 3

找找有没有库函数可用，VHDL里有二进制转十进制的