求用Verilog写个对应的testbench，指令寄存器的testbench。

Question

以下是我的指令寄存器verilog代码
`timescale 1ns/1ps
module register(opc_iraddr,data,ena,clk,rst);
output [15:0]opc_iraddr;
input [7:0]data;
input ena,clk,rst;
reg [15:0]opc_iraddr;
reg state;
always @(posedge clk)
begin
if (rst)
begin
opc_iraddr<=16'b0000_0000_0000_0000;
state<=1'b0;
end
else if (ena)
casex(state)
1'b0:begin
opc_iraddr[15:8]<=data;
state<=1;
end
1'b1:begin
opc_iraddr[7:0]<=data;
state<=0;
end
default:begin
opc_iraddr[15:0]<=16'bx;
state<=1'bx;
end
endcase
else state<=1'b0;
end
endmodule

Answer 1

`timescale 1ns/1ps
module reg_tb;
reg [7:0] data_i;
reg ena_i;
reg clk;
reg rst_n;
reg [7:0] cnt;
wire [15:0]opc_iraddr_o;

register DUT(
.clk ( clk ),
.rst ( ~rst_n ),
.data ( data_i ),
.ena ( ena_i ),
.opc_iraddr ( opc_iraddr_o )
);

initial
begin
clk = 0;
rst = 0;
ena_i = 0;
cnt = 0;
data_i = 0;
#50
rst_n = 1;
end

always #5 clk = ~clk;

always @( posedge clk or negedge rst_n )begin
if( !rst_n )
cnt <= 8'h0;
else
cnt <= cnt + 1'b1;
end

always @( posedge clk or negedge rst_n )begin
if( !rst_n )
data <= 8'h0;
else if( cnt = 8'h01 )
data <= 8'h55;
else if( cnt = 8'h10 )
data <= 8'haa;
else
;
end

initial
begin
#50
ena_i = 1;
#50
ena_i = 0;
#100
ena_i = 1;
#100
ena_i = 0;
#10
ena_i = 1;
#10
ena_i = 0;
#10000
rst_n = 1;
$stop;
end
//现写的，没仿过，不过问题不大。。。功能简单