高分急求Verilog写个指令寄存器测试平台代码testbench，求高水，立即采纳。

Question

被测代码如下，求testbench代码
`timescale 1ns/1ns
module register(opc_iraddr,data,ena,clk,rst);
output [15:0]opc_iraddr;
input [7:0]data;
input ena,clk,rst;
reg [15:0]opc_iraddr;
reg state;
always @(posedge clk)
begin
if (rst)
begin
opc_iraddr<=16'b0000_0000_0000_0000;
state<=1'b0;
end
else if (ena)
casex(state)
1'b0:begin
opc_iraddr[15:8]<=data;
state<=1;
end
1'b1:begin
opc_iraddr[7:0]<=data;
state<=0;
end
default:begin
opc_iraddr[15:0]<=16'bx;
state<=1'bx;
end
endcase
else state<=1'b0;
end
endmodule

Answer 1

`timescale 1ns/1ns
module register_tb();
reg clk,rst;
reg ena;
reg [7:0] data;
wire [15:0] opc_iraddr;

initial begin
clk = 0;
rst = 1;
ena = 0;
# 100 rst = 0;
end

always # 10 clk = ~clk;

register dut(
.opc_iraddr(opc_iraddr),
.data(data),
.ena(ena),
.clk(clk),
.rst(rst)
);

always @ ( posedge clk or posedge rst )
begin
if ( rst ) begin
data <= 0;
ena <= 0;
end
else begin
data <= data + 1;
case ( data )
10,11,12,13,14:ena <= 1;//在输入data为10,11,12,13,14置高ena，想改加数字
default:ena <= 0;
endcase
end
end
endmodule

Answer 2

`timescale 1ns/1ns
module testregister();
wire [15:0]iraddr;
wire [7:0]dat;
reg [15:0]rdat;
reg en;
reg clk;
reg rst;
reg step;
initial begin
clk <= 1'b0;
en <= 1'b0;
rst <= 1'b1;
rdat <= 16'b0;
step <= 1'b0;
end
assign dat = step?rdat[15:8]:rdat[7:0];
always #100 clk <= ~clk;

always @(posedge clk)
begin
step <= ~step;
if(en & step)
rdat <= rdat + 1'b1;
end
always @(posedge clk)
begin
if(rst) begin
if(step)
rst <= 1'b0;
end
else
en <= 1'b1;
end
register u0(.opc_iraddr(iraddr),.data(dat),.ena(en),.clk(clk),.rst(rst));
endmodule本回答被网友采纳