新手求助，verilog hdl要设计一个带异步清零和异步预置的8 位二进制加法计数器，麻烦看看代码哪儿错了。。

Question

想了半天了，编译错误里面总是提示
Error (10170): Verilog HDL syntax error at Verilog1.v(11) near text ?
Error (10170): Verilog HDL syntax error at Verilog1.v(11) near text "?; expecting ")", or "?", or binary operator

这是代码
module counter(qout,cout,data,load,reset,clk);
output[7:0] qout;
output cout;
input[7:0] data;
input load,reset,clk;
reg[7:0] qout;
reg cout;
always @ (posedge clk)
if(reset) qout = 0;
else if(load) qout = data;
else if (qout==8’b11111111)
begin qout=0; cout=1; end
else
begin qout=qout+1; cout=0; end
endmodule

Answer 1

8’b11111111，那个 8与b之间的符号打错了，应该是单引号‘ ，你改下在试试，而且你的代码是同步复位和置位的，不是异步的，要想实现异步需要将always @ (posedge clk)

改成always @ (posedge clk or posedge reset or posedge load)

例外建议在时序的逻辑内部qout=0; cout=1；这些等式都写成qout<=0; cout<=1;