Verilog HDL语言释义

Question

我有几段Verilog程序，我自己会用，但是我不知道每段程序是什么意思，希望有能看得懂的帮我在每行后面解释一下意思。应该很简单吧。
module xianshi(clk,xinhao,seg,dig,gao,set );
input clk,xinhao;
output reg [6:0] seg;
output reg [5:0] dig;
reg [5:0] c_fen,c_miao,c_shi;
reg [3:0] s;
wire [3:0] miao_1,miao_2,fen_1,fen_2,shi_1,shi_2;
reg [2:0] count;
reg [1:0] data[18:0];
reg [4:0] state;
reg zuo,did;
integer j,c_wu,i,n;
output reg gao;
output reg set;
fenpin1khz myfenpin1khz(clk,clk1khz);
fenpin1hz myfenpin1hz(clk1khz,clk1hz);
initial

begin
state=0;
zuo=0;
did=0;
j=0;
i=0;
n=0;
end
always @(posedge clk1khz)
gao=1;
always @(posedge clk1khz) //judge xinhao blank
begin
if(xinhao==0)
n=n+1;
if(xinhao==1&&n<920)
n=0;
if(n>1500)
zuo<=1;
end
always @(posedge xinhao ) //judge xinhao first posedge
if(zuo==1)
did<=1;

always @(posedge clk1khz )
if(did==1)
begin
if(i==1000)
i=1;
else
i=i+1;
end
always @(posedge clk1khz ) //change state
if(i==1000)
begin
if(state==19)
state<=0;
else
state<=state+1;
end
always @(posedge clk1khz) //save data

begin
if(state>=0&&state<=18&&did==1)
begin
if(xinhao==1)
j=j+1;
else
begin
if(j>80&&j<120)
data[state]=0;
else if(j>180&&j<220)
data[state]=1;
else if(j>280&&j<320)
data[state]=2;
else if(j>380&&j<420)
data[state]=3;
j=0;
end
end
end
always @(posedge clk1hz)

begin
if(state==18)
begin
set<=1;
c_wu=data[9];
c_fen <=data[4]*16+data[5]*4+data[6];
c_miao <=data[0]*20+19;
if(c_wu>1)
c_shi=data[2]*4+data[3]+12;
else
c_shi=data[2]*4+data[3];
if(c_shi == 24 || c_shi ==12)
c_shi=c_shi - 12;
end
else
begin

set<=0;
if(c_miao==59)
begin
if(c_fen==59)
begin
if(c_shi==23)
begin
c_miao <=0;
c_fen <=0;
c_shi <=0;
end
else
begin
c_miao <=0;
c_fen <=0;
c_shi <=c_shi+1;
end
end
else
begin
c_miao <=0;
c_fen <=c_fen+1;
end
end
else
c_miao <=c_miao+1;
end
end
always @(posedge clk1khz)

begin
if(count==3'b101)
count<=0;
else
count<=count+1;
end
div_rill(c_miao,10,miao_1,miao_2);

div_rill(c_fen,10,fen_1,fen_2);
div_rill(c_shi,10,shi_1,shi_2);
always @(count)

begin
case(count)
0:begin dig=8'b000001;s=miao_2;end
1:begin dig=8'b000010;s=miao_1;end
2:begin dig=8'b000100;s=fen_2;end
3:begin dig=8'b001000;s=fen_1;end
4:begin dig=8'b010000;s=shi_2;end
5:begin dig=8'b100000;s=shi_1;end
endcase
end
always @(s)

begin
case(s)
0:seg=7'b0111111;
1:seg=7'b0000110;
2:seg=7'b1011011;
3:seg=7'b1001111;
4:seg=7'b1100110;
5:seg=7'b1101101;
6:seg=7'b1111101;
7:seg=7'b0000111;
8:seg=7'b1111111;
9:seg=7'b1101111;
default:seg=7'bx;
endcase
end
endmodule

Answer 1

module count24(Rd,EN,CLK,Qh,Ql,C);
input Rd,EN,CLK;
output [3:0]Qh,Ql;----------------------------------输出，Qh代表十位，Qi代表个位
output C; --------------------------------------------进位标志，当Qh与QI总和达到24时，C置1
reg [3:0]Qh,Ql;
reg C;-------------------------------------------------声明QhQIC为寄存器变量，说明应用于时序逻辑
initial
begin
Qh=4'd0;Ql=4'd0;C=0;
end ------------------------------从initial到end表示初始化赋值，这段语句不会被综合，用于仿真
always @ (posedge CLK)
begin
if(EN==1)------------------------使能，当EN为高电平时才执行下面的程序
begin
if(Rd==0)
begin
Qh=4'd0;Ql=4'd0;C=0; --------------当Rd为0时，QhQIC设置为0，说明Rd是复位信号
end
else if(Qh<4'd2&&Ql<4'd9)
Ql=Ql+1; ----------------------------------当Qh小于2，QI小于9时，时钟上升沿到来时QI加1
else if(Qh<4'd2&&Ql==4'd9)
begin
Qh=Qh+1;Ql=4'd0; ------------当Qh小于2，且QI已等于9，Qh十位进位加1，QI恢复0
end
else if(Qh==4'd2&&Ql<4'd3)
Ql=Ql+1; ---------------------------当Qh等于2，QI小于3，QI加1
else -------------------------------------若前面条件不满足，将QhQIC均设置为0
begin
Qh=4'd0;Ql=4'd0;C=0;
end

if(Qh==4'd2&&Ql==4'd3) ----------------若为23，C进1
C=1;
end
end
endmodule

Answer 2

D[5:0]相当于ram有多少个单元

reg[5:0]就是每个单元的位宽