求好心的大神！！怎样用FPGA实现将任一六位二进制数转换成十进制数在LED上动态显示！

Question

怎样用FPGA实现将任一六位二进制数转换成十进制数在LED上动态显示！我知道C怎么实现。但不知道FPGA咋办！谢谢。

Answer 1

思路:
六位二进制数->2位BCD->七段译码器转为数码管显示

附一个 8位BCD码转换程序供你参考(y0~y7是8位BCD码输出(每个4位),din是二进制输入),位数宽度自己改吧,七段译码器也附上了,这个不用改了,连线上就能用了.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity B_BCD is
port(clk:in std_logic;
din:in std_logic_vector(26 downto 0);
y0,y1,y2,y3,y4,y5,y6,y7:out std_logic_vector(3 downto 0));
end B_BCD;
architecture behav of B_BCD is
type state is (s0,s1,s2);
signal present_state:state;
signal mid_in:std_logic_vector(26 downto 0);
signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(3 downto 0);
begin

process(clk)is
begin
if clk'event and clk='1' then
mid_in<=din;
present_state<=s0;

case (present_state) is
when s0=>
d0<="0000";d1<="0000";d2<="0000";d3<="0000";d4<="0000";d5<="0000";d6<="0000";d7<="0000";
present_state<=s1;
when s1=>
if mid_in>="100110001001011010000000" then mid_in<=mid_in-"100110001001011010000000";
d7<=d7+1;
present_state<=s1;
elsif mid_in>="000011110100001001000000" then mid_in<=mid_in-"000011110100001001000000";
d6<=d6+1;
present_state<=s1;
elsif mid_in>="000000011000011010100000" then mid_in<=mid_in-"000000011000011010100000";
d5<=d5+1;
present_state<=s1;
elsif mid_in>="000000000010011100010000" then mid_in<=mid_in-"000000000010011100010000";
d4<=d4+1;
present_state<=s1;
elsif mid_in>="000000000000001111101000" then mid_in<=mid_in-"000000000000001111101000";
d3<=d3+1;
present_state<=s1;
elsif mid_in>="000000000000000001100100" then mid_in<=mid_in-"000000000000000001100100";
d2<=d2+1;
present_state<=s1;
elsif mid_in>="000000000000000000001010" then mid_in<=mid_in-"000000000000000000001010";
d1<=d1+1;
present_state<=s1;
elsif mid_in>="000000000000000000000001" then
mid_in<=mid_in-"000000000000000000000001";

d0<=d0+1;
present_state<=s1;

else
present_state<=s2;
end if;

when s2=>

y0<=d0;y1<=d1;y2<=d2;y3<=d3;y4<=d4;y5<=d5;y6<=d6;y7<=d7;
present_state<=s0;
when others=>
present_state<=s0;
end case;
end if;
end process;
end behav;

--七段译码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_7_part IS
PORT(i3,i2,i1,i0:IN STD_LOGIC;
a,b,c,d,e,f,g:OUT STD_LOGIC);
END decoder_7_part;
ARCHITECTURE rtl OF decoder_7_part IS
SIGNAL indata:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal outdata:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
process(indata)
begin
indata<=i3&i2&i1&i0;

CASE indata IS
WHEN "0000"=>outdata<="1111110";
WHEN "0001"=>outdata<="0110000";
WHEN "0010"=>outdata<="1101101";
WHEN "0011"=>outdata<="1111001";
WHEN "0100"=>outdata<="0110011";
WHEN "0101"=>outdata<="1011011";
WHEN "0110"=>outdata<="0011111";
WHEN "0111"=>outdata<="1110000";
WHEN "1000"=>outdata<="1111111";
WHEN "1001"=>outdata<="1111011";
when others=>outdata<="0000000";
END CASE;
a<=outdata(0);
b<=outdata(1);
c<=outdata(2);
d<=outdata(3);
e<=outdata(4);
f<=outdata(5);
g<=outdata(6);

END process;
end;

Answer 2

我用的FPGA是altera公司的，你可以使用nios II，在FPGA中嵌入CPU核，就可以用C编程了，和单片机差不多，但是有一些固定的语法而已。本回答被提问者采纳

Answer 3

不搞这个很久了，所以只能给你一点简单的建议，六位二进制最多用两个LED来显示，所以先把6位二进制转换为十进制得到你要显示的十位数值和个位数值，然后将这两个值传送给LED寄存器追问

我的问题就在这里。。怎么比如'111111'十进制应该是63吧。这个转换的过程我就不知道咋办了

追答

我记得寄存器是不是可以取最低位？设置变量s，先取最低位假设为s0,让s=s0；然后寄存器右移一位取最低位s0，让s= s+s0*2；然后寄存器再右移一位取最低位，s=s+s0*4。。。你可以用一个变量i标记右移次数，然后s=s+s0*2^i，这样行不行？

不过貌似6位二进制转换为2个七段译码器在FPGA上应该用组合逻辑来实现吧？？？

Answer 4

1 //6-bit binary to 2-digit BCD
2 module b2b(a,ones,tens);
3 input [5:0]a;
4 output [3:0]ones,tens;
5
6 wire [3:0]c1,c2,c3;
7 wire [3:0]d1,d2,d3;
8
9 assign d1={1'b0,a[5:3]};
10 assign d2={c1[2:0],a[2]};
11 assign d3={c2[2:0],a[1]};
12 add3 m1(d1,c1);
13 add3 m2(d2,c2);
14 add3 m3(d3,c3);
15 assign ones={c3[2:0],a[0]};
16 assign tens={1'b0,c1[3],c2[3],c3[3]};
17
18 endmodule
19
20 //add3.v
21 module add3(in,out);
22 input [3:0] in;
23 output [3:0] out;
24 reg [3:0] out;
25
26 always @ (in)
27 case (in)
28 4'b0000: out <= 4'b0000;
29 4'b0001: out <= 4'b0001;
30 4'b0010: out <= 4'b0010;
31 4'b0011: out <= 4'b0011;
32 4'b0100: out <= 4'b0100;
33 4'b0101: out <= 4'b1000;
34 4'b0110: out <= 4'b1001;
35 4'b0111: out <= 4'b1010;
36 4'b1000: out <= 4'b1011;
37 4'b1001: out <= 4'b1100;
38 default: out <= 4'b0000;
39 endcase
40 endmodule
41
42 //top_level file
43 module binary2bcd(SW,HEX1,HEX0);
44 input [5:0]SW;
45 output [0:6]HEX1,HEX0;
46
47 wire [3:0]ones,tens;
48
49 b2b u3(SW,ones,tens);
50 btd u1(ones,HEX0);
51 btd u2(tens,HEX1);
52
53 endmodule
这是代码， 已近测试过了，输入6位2进制数，输出两位十进制数。用verilog语言写的

Answer 5

用verliog，跟C差不多的语言