用verilog程序设计一个具有异步清零和同步置数功能的十进制可逆计数器

Question

如题所述

Answer 1

嗯

Answer 2

module m10_counter(output reg[3:0]Q,
input ce,cp,cr);
always @(posedge cp,negedge cr)
if(~cr)Q=4'b0000; //????
else if(ce) //ce=1,
begin
if(Q>=4'b1001)
Q<=4'b0000;
else Q<=Q+1'b1;
end
else Q<=Q; //??????
endmodule