第1个回答 2011-06-30
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DATA IS
PORT(
a,b,c: IN STD_LOGIC;
c: OUT STD_LOGIC);
END DATA;
ARCHITECTURE Behave OF DATA IS
BEGIN
LABEL:BLOCK
VARRIBLE tmp1,tmp2,tmp3:STD_LOGIC;
BEGIN
tmp1:=a and b;
tmp2:=c and (not b);
tmp3:=tmp1 or tmp2;
y<=tmp3;
END BLOCK LABEL;
END Behave;
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