verilog设计

Question

设计一个模块，输入为时钟clk, 输出信号out为时钟的频率1/4；

Answer 1

module quat_div( clk, rst_n, out);
input clk, rst_n; // rst_n是异步复位信号，低电平有效
output out;

reg [1:0] cnter;
assign out = cnter[1];

always @ (posedge clk or negedge rst_n)
begin
if( !rst_n )
cnter <= 2'd0;
else
cnter <= cnter + 2'd1;
end

endmodule