verilog状态机检测001序列。。。。如果写的全，加分。。。。考试要用。。。最好能划一下图表。。有分

Question

如题所述

Answer 1

module fsm(clk,x,reset,z);

input x,reset,clk;

output z;

reg z;

reg[1:0] state;//状态

parameter s0=2'b00,s1=2'b01,s2=2'b10;

always@(posedge clk)

begin

if（reset）

state<=s0;

else

begin

case(state)

s0:begin if(x) begin state<=s0;z<=0;end

               else begin state<=s1;z<=0;end

     end

s1:begin if(x) begin state<=s0;z<=0;end

               else begin state<=s2;z<=0;end

     end

s2:begin if(x) begin state<=s0;z<=1;end

               else begin state<=s2;z<=0;end

     end

endcase

end

end

endmodule

Answer 2

odule fsm(clk,x,reset,z);
input x,reset,clk;
output z;
reg z;
reg[1:0] state;//状态
parameter s0=2'b00,s1=2'b01,s2=2'b10;
always@(posedge clk)
begin
if（reset）
state<=s0;
else
begin
case(state)
s0:begin if(x) begin state<=s0;z<=0;end
else begin state<=s1;z<=0;end
end
s1:begin if(x) begin state<=s0;z<=0;end
else begin state<=s2;z<=0;end

endcase
end
end