module test( input wire rst_n // Reset, Active Low ,input wire clk // // Add other inputs and outputs here // ); integer k; parameter n = 10; // set the value of n here reg signed [20:0] e[0:n-1]; always @(posedge clk or negedge rst_n) begin if(~rst_n) begin for(k=0;k<n;k=k+1) e[k] <= 21'h0; // set initial value of matrix to all zero here end else begin // change the value of e here normally end end