Verilog 代码求救 我要做 5阶的随机数发生器 5个D触发器 和一个异或门的 那种最简单的 但是出不来波形救救

Question

module lfsr1(out,clk, reset);

output [3:0] out;
input clk, reset;
reg [4:0] out;
reg pp;
wire DXOR;

xor X1(DXOR,out[2],out[4]);

always @(posedge clk or negedge reset)
begin
if (!reset)
begin
pp=0;
out=1;
end
else
begin
case(pp)
0: out[0]<=DXOR;
1: out[1]<=out[0];
2: out[2]<=out[1];
3: out[3]<=out[2];
4: out[4]<=out[3];
endcase
pp=pp+1;
end
if(pp==4)
begin
pp=0;
end
end
end
endmodule // End Of Module counter

(3)test文件
`timescale 1ns/100ps
`include "lfsr1.v"
module tb_lfsr1;
reg clk_reg, reset_reg;
wire[4:0] out_wire;

initial
begin
clk_reg=0;
reset_reg=1;
#2; reset_reg=0;
#120; reset_reg=1;
#3000; $stop;
end

always #50 clk_reg=~clk_reg;

lfsr1 d(.out(out_wire),.clk(clk_reg), .reset(reset_reg));
endmodule

Answer 1

module lfsr1(out,clk, reset);

output [3:0] out;
input clk, reset;
reg [4:0] out;

wire DXOR;

xor X1(DXOR,out[2],out[4]);

always @(posedge clk or negedge reset)
if (!reset)
out=5'd1;
else
out <= {out[3:0], DXOR};

endmodule // End Of Module counter