It is possible to have two separate memory systems for a hardward archiitecture.As long as date and instructions can be fed in at the same time.then it doesn't matter whether it comes from a cache or memory.But there are problems with this. Comolers generally.embed data(literal pools) within the cide,and it is often also necessary to be able to write to the instruction memory space,for example in the case of self modifying code,or,if an ARM debugger is used,to set software breakpoints in memory.If there are two completely separate,isolated memery systems,this is not possible.There must be some kind of bridge between the memory systems to allow this.
Using a simple,unfined memory system together with a Harvard architecture is highly inefficient.Vnless it is possible to feed data into both binsses at the same time,it might be better to use a ron.Neumann architecture processor.
Use of caches
At higher clock speeds,caches are useful as the memory speed is proportionally slower.Harvard architectures tend to be targeted at higher performance systems,and so caches are nearly always used in such systems.Von Neumann architectures.usually have a single unfined cache,which stores,both instructions and date.The proportion of each in the cache is variable which may be a good thing.It would in prineiple be possible to have separate instruction and data caches,storing data and instructious sepurately.This probably would not be very useful as it would only be possible to everaccess one cache at a time.
Caches for Hardward archhitectures are very useful.Such a system would have separate caches for each bus.Trying to use a shared cache on a Hardward architecture would be very inefficieue since then.only one bus can be fed at a time.Having two caches means.it is possible to feed both buses simultansously...exactly what is necessary for a Harvard architecture.