EDA用VHDL编写一个多功能电路，可实现与，或，异或，同或功能，谢谢了～

Question

如题所述

Answer 1

ENTITY lu IS

GENERIC (n:Positive :=8);

PORT(a,b:IN bit_vector(n-1 DOWNTO 0);

op:IN bit_vector(1 DOWNTO 0);

y:OUT bit_vector(n-1 DOWNTO 0));

END lu;
ARCHITECTURE bhv OF lu IS
BEGIN
PROCESS(a,b,op)

BEGIN

CASE op IS

WHEN "00" => y <= a AND b;

WHEN "01" => y <= a OR b;

WHEN "10" => y <= a XOR b;

WHEN "11" => y <= a XNOR b;

END CASE;

END PROCESS;

END bhv;