module run_led(clk,rst,led); //module port input clk;//system clock input rst;//system reset
output [7:0] led; // 8bits led
reg [7:0] led; reg [25:0] count; always @ (posedge clk ) begin if(rst || count[25]==1) begin count<=26'b0; end else count<=count+1; end always @ (posedge clk) begin if(rst) led<=8'b0000_0001; else begin if(count[25]==1) begin