Although the mosfet design could certainly be further optimised to improve overall efficiency, here we have focused on evaluating one system with particular parameters, so as to assess the impact of varying the active areas and inductor size. We can see that the generation efficiency decreases with increasing device size, while the conversion efficiency initially increases and then decreases, as the efficiency is dominated first by conduction and then by charge sharing losses. The optimum area for conversion efficiency increases with decreasing inductance, because conduction losses become relatively more important. From Figure IO and Figure 12 we can thus conclude that high inductance values are critical to achieving good circuit performance. Accordingly, the interesting regions of Figure 12 are to the left of the maxima, for example at 30 cells and IO pH. Figure IO shows that a conversion circuil using 30- cell devices does not significantly harm generation. It should also he mentioned that the parasitic capacitance of the inductors may have a significant impact, and this has yet to he analysed.
Leakage at the rated voltage is around 3 nA which would only become relevant for flight times in excess of 0.1 s. Despite the low charge levels, it is necessary to have good peak-current on-state performance and high voltage blocking;
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therefore, it appears that designing a specific power device more suitable for peak currents would allow the shrinking of generator and inductor sizes. The generator would then occupy less area on the chip which may be necessary for the technology to become viable.
It may also he beneficial to scale the high- and low-side mosfets individually, as the high- and low-side device areas affect generation and conversion efficiencies differently.