用Verilog HDL设计一个4位串_并转换器，需要程序和一定的注释

Question

如题所述

Answer 1

module s2p(clk,rst_n,sdi,pdo);
input clk ; // clock signal for serial data input
input rst_n ; // system reset signal,negative value
input sdi ; // serial data input,posedge clock signal value,high significance bit input first
output[3:0] pdo ; // parallel data output

reg[3:0] pdo ;
always@(posedge clk)
begin
// reset signal value
if(rst_n==1'b0)
begin
pdo<=4'b0000 ;
end

// reset signal is not value,module work
else
begin
pdo[3:0]<={pdo[2:0],sdi} ; // shift register value
end
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