Verilog HDL 数学符号^和||的意思

Question

module ch4ex1(A,B,C,Y);
input A,B,C;
output Y;
reg Y;
always @(A or B or C)
if(A == 0)
if (B||C == 1)
Y = 1;
else
Y = 0;
else if(B^C == 1)
Y = 1;
else
Y = 0;
endmodule

Answer 1

^ 逻辑与
|| 逻辑或本回答被提问者采纳

Answer 2

^ 是异或 错误答案太误人子弟了

Answer 3

^ 逻辑与
|| 逻辑或本回答被提问者采纳

Answer 4

^ 是异或 错误答案太误人子弟了