用D触发器实现2倍分频的Verilog描述？

Question

如题所述

Answer 1

module d_ff(clk,data_out,reset);
input clk,reset;
output data_out;
reg data_out;
reg data_in;
always @(posedge clk)
begin
if (!reset)
data_out=0;
else
begin
data_in=~data_out;
data_out=data_in;

end
end
//always @(posedge clk)
// data_in<=~data_out;
endmodulemodule d_ff_tb;
reg clk,reset;
wire data_out;
initial
begin
clk=1;
reset=0;
#40 reset=1;
end

always #10 clk=~clk;
// initial
//data_in=0;
//always #10 data_in=~data_in;
d_ff U1 (clk,data_out,reset);
endmodule

Answer 2

module divide2( clk , clk_o, reset);
input clk , reset;
output clk_o;
wire in;
reg out ;
always @ ( posedge clk or posedge reset)
if ( reset)
out <= 0;
else
out <= in;
assign in = ~out;
assign clk_o = out;
endmodule本回答被网友采纳