高手来看看这个verilog串并转换状态机程序的时序仿真

Question

有四位前导码，即前四位是连续1时从第五位开始串并转换，共转换3位
功能仿真可以通过，时序仿真无结果，请高手们看看啊
程序如下：
module serial_in(
input sys_clk,
input sys_rst,
input data_input_1,
output reg [2:0] xlat_address_port_1
);

reg [2:0] shift_register;
reg [2:0] count;
reg [4:0] current_state, next_state;
reg flag;

parameter [4:0] s0=5'b00001, s1=5'b00010, s2=5'b00100, s3=5'b01000,s4=5'b10000;

always @ (posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
begin
current_state<=s0;
end
else
current_state<=next_state;
end

always @ (current_state or data_input_1 or flag)
begin
next_state=3'bxxx;
case(current_state)
s0: if(data_input_1==1)
begin next_state=s1; end
else
begin next_state=s0; end
s1: if(data_input_1==1)
begin next_state=s2; end
else
begin next_state=s0; end
s2: if(data_input_1==1)
begin next_state=s3; end
else
begin next_state=s0; end
s3: if(data_input_1==1)
begin next_state=s4; end
else
begin next_state=s0; end
s4: if(flag)
begin next_state=s0; end
else
begin next_state=s4; end
endcase
end

always @ (posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
begin
xlat_address_port_1<=3'b000;
shift_register<=3'b0;
count<=3'b0;
flag<=0;
end
else begin
xlat_address_port_1<=3'b0;
case(current_state)
s0,s1,s2,s3: begin
xlat_address_port_1<=3'b0;
flag<=0;
count<=3'b000;
end
s4: begin
count<=count+3'b1;
shift_register[0]<=data_input_1;
shift_register[1]<=shift_register[0];
shift_register[2]<=shift_register[1];

if(count==3'b011)
begin
xlat_address_port_1[2:0]<=shift_register[2:0];
flag<=1;
end
else
xlat_address_port_1<=3'b000;
end
endcase
end
end
endmodule
就是状态机出问题了
当四个前导码识别后，不能按照设计进入s4状态，也就是开始串并转换状态，请问大侠要怎么改动程序呢

Answer 1

这种情况一般都是状态机出问题了
data_input_1信号在在S3的情况下过早为0,会导致current_state不能进入S4状态.data_input_1必须值到下一个时钟周期开始时也为1,保证next_state最终为S4,这样才能在上升沿加载到current_state寄存器中,因此这个设计对于前导码之后第1位为0是失效的,第一位为1则可以运行,你可以做个实验验证一下.
解决方案:用个寄存器先对输入信号同步采样一下.

Answer 2

感觉没什么问题 我测试了下 输入串码1111 101
你可以用我的tb跑跑看
-----------------------
module test_test();
reg sys_clk ;
reg sys_rst ;

reg data_input_1;
wire [2:0] xlat_address_port_1;

always #5 sys_clk = ~sys_clk;

initial begin
sys_clk = 1'b0;
sys_rst = 1'b0;
data_input_1 = 1'b0;
#10 sys_rst = 1'b1;
#5;
#10 data_input_1 = 1'b1;
#10 data_input_1 = 1'b1;
#10 data_input_1 = 1'b1;
#10 data_input_1 = 1'b1;
#10 data_input_1 = 1'b1;
#10 data_input_1 = 1'b0;
#10 data_input_1 = 1'b1;
#10 data_input_1 = 1'b0;
end

serial_in serial_in(
.sys_clk (sys_clk ),
.sys_rst (sys_rst ),
.data_input_1 (data_input_1 ),
.xlat_address_port_1 (xlat_address_port_1)
);

endmodule本回答被提问者采纳